library ieee;
use ieee.std_logic_1164.all;

entity flopr is
    generic(value : integer := 32);
    port (
            d   :   in std_logic_vector((value - 1) downto 0);
            q   :   out std_logic_vector((value - 1) downto 0);
            rst :   in  std_logic;
            clk :   in  std_logic
          );
end entity;

architecture flopr_generic_arch of flopr is
    begin
        process (clk, rst) begin
            for i in (value - 1) downto 0 loop
                if (rst = '1') then
                    q(i) <= '0';
                elsif (clk'event and clk='1') then
                    q(i) <= d(i);
                end if;
            end loop;
        end process;
end architecture;
